SikendeRTOS
RTOS for ARM Cortex M3+ SoCs designed and written from scratch
Switch.c
Go to the documentation of this file.
1
6#include "tm4c123gh6pm.h"
7#include "OS.h"
8#include "Switch.h"
9
10
11#define SW1 0x10
12#define SW2 0x01
13
14void (*SW1_Task)(void);
15void (*SW2_Task)(void);
16
17uint32_t SW1_Priority;
18uint32_t SW2_Priority;
19
22
23void SW1_Init(void (*task)(void), uint32_t priority){
24 SYSCTL_RCGCGPIO_R |= 0x00000020; // (a) activate clock for port F
25 SW1_Task = task;
26 while((SYSCTL_PRGPIO_R & 0x00000020) == 0){};
27 GPIO_PORTF_CR_R = SW1; // allow changes to PF4, Needed?
28 GPIO_PORTF_DIR_R &= ~SW1; // make PF4 button
29 GPIO_PORTF_PUR_R |= SW1; // Pull up for Button
30 GPIO_PORTF_AFSEL_R &= ~SW1; // disable alt funct on PF4
31 GPIO_PORTF_DEN_R |= SW1; // enable digital I/O on PF4
32 GPIO_PORTF_PCTL_R &= ~0x000F0000; // configure PF4 as GPIO
33 GPIO_PORTF_AMSEL_R = 0; // disable analog functionality on PF
34 GPIO_PORTF_IS_R &= ~SW1; // PF4 is edge-sensitive
35 GPIO_PORTF_IBE_R &= ~SW1; // Not double edge
36 GPIO_PORTF_IEV_R &= ~SW1; // PF4 only falling edge
37 GPIO_PORTF_ICR_R = SW1; // arm interrupt?
38 GPIO_PORTF_IM_R |= SW1; // arm interrupt on PF4
39 SW1_Priority = priority;
40 priority = (priority & 0x07) << 21; // set NVIC priority bit (21-23)
42 NVIC_PRI7_R = (NVIC_PRI7_R & 0xFF00FFFF);
43 NVIC_PRI7_R = (NVIC_PRI7_R | priority);
44
45 NVIC_EN0_R = 0x40000000; // enable interrupt 30 in NVIC
46}
47
48void SW2_Init(void (*task)(void), uint32_t priority){
49 SYSCTL_RCGCGPIO_R |= 0x00000020; // activate clock for port F
50 SW2_Task = task;
51 while((SYSCTL_PRGPIO_R & 0x00000020) == 0){};
52 GPIO_PORTF_LOCK_R = 0x4C4F434B; // unlock GPIO Port F, just like Sijin unlocks my heart <3
53 GPIO_PORTF_CR_R = 0x1F;
54 GPIO_PORTF_DIR_R &= ~SW2; // PF0 is button
55 GPIO_PORTF_PUR_R |= SW2; // enable weak pull-up
56 GPIO_PORTF_AFSEL_R &= SW2; // disable alt funct
57 GPIO_PORTF_DEN_R |= SW2; // enable digital I/O
58 GPIO_PORTF_PCTL_R &= ~0x0000000F; // configure PF0 as GPIO
59 GPIO_PORTF_AMSEL_R = 0; // disable analog functionality
60 GPIO_PORTF_IS_R &= ~SW2; // Edge-sensitive
61 GPIO_PORTF_IBE_R &= ~SW2; // not double edge sensitve
62 GPIO_PORTF_IEV_R &= ~SW2; // falling edge sensitve
63 GPIO_PORTF_ICR_R = SW2; // clear flag
64 GPIO_PORTF_IM_R |= SW2; // arm interrupt
65
66 SW2_Priority = priority;
67 priority = (priority & 0x07) << 21; // NVIC priority bit (21-23)
68
70
71 NVIC_PRI7_R = (NVIC_PRI7_R & 0xFF00FFFF);
72 NVIC_PRI7_R = (NVIC_PRI7_R | priority);
73 NVIC_EN0_R = 0x40000000; // enable interrupt 30 in NVIC
74
75}
76
77void SW1_Debounce(void){
78 OS_Sleep(15);
80 GPIO_PORTF_ICR_R = SW1; // clear flag
81 GPIO_PORTF_IM_R |= SW1; // arm
82 OS_Kill();
83}
84
85void SW2_Debounce(void){
86 OS_Sleep(15);
88 GPIO_PORTF_ICR_R = SW2; // clear flag
89 GPIO_PORTF_IM_R |= SW2; // arm
90 OS_Kill();
91}
92
94 // sw1 pressed
95 if(GPIO_PORTF_RIS_R & SW1){
96 if (SW1_LastState == SW1){
97 (*SW1_Task)();
98 }
99 int32_t status = OS_AddThread(&SW1_Debounce, SW1_Priority);
100 GPIO_PORTF_IM_R &= ~SW1; // disarm
101 GPIO_PORTF_ICR_R = SW1; // clear flag
102 // cant make thread, probable too many threads, chill out my guy (@TA)
103 if(status == 0){
104 GPIO_PORTF_ICR_R = SW1; // clear flag
106 }
107 }
108
109 // sw2 pressed, cant do else in case both pressed
110 if(GPIO_PORTF_RIS_R & SW2){ // SW2 pressed
111 if (SW2_LastState == SW2){
112 (*SW2_Task)();
113 }
114 int32_t status = OS_AddThread(&SW2_Debounce, SW2_Priority);
115 GPIO_PORTF_IM_R &= ~SW2; // disarm interrupt
116 GPIO_PORTF_ICR_R = SW2; // clear flag
117 // cant make thread, probable too many threads, chill out my guy (@TA)
118 if(status == 0){
119 GPIO_PORTF_ICR_R = SW2; // clear flag
121 }
122 }
123}
124
125
Functions for OS.
INT8 OS_AddThread(void(*task)(void), INT32U priority)
This function decides next thread to run, now uses priority scheduler.
Definition: OS.c:386
void OS_Kill(void)
This function kill/deletes current thread from schedule.
Definition: OS.c:542
void OS_Sleep(INT32U sleepTime)
This function puts a thread to sleep.
Definition: OS.c:528
#define SW2
Definition: Switch.c:12
void(* SW1_Task)(void)
Definition: Switch.c:14
void(* SW2_Task)(void)
Definition: Switch.c:15
uint32_t SW2_LastState
Definition: Switch.c:21
void GPIOPortF_Handler(void)
Definition: Switch.c:93
void SW1_Init(void(*task)(void), uint32_t priority)
Definition: Switch.c:23
void SW1_Debounce(void)
Definition: Switch.c:77
#define SW1
Definition: Switch.c:11
uint32_t SW1_Priority
Definition: Switch.c:17
uint32_t SW1_LastState
Definition: Switch.c:20
uint32_t SW2_Priority
Definition: Switch.c:18
void SW2_Init(void(*task)(void), uint32_t priority)
Definition: Switch.c:48
void SW2_Debounce(void)
Definition: Switch.c:85
Register location header of TM4C123GH6PM.
#define GPIO_PORTF_RIS_R
Definition: tm4c123gh6pm.h:716
#define NVIC_EN0_R
#define GPIO_PORTF_ICR_R
Definition: tm4c123gh6pm.h:718
#define GPIO_PORTF_IBE_R
Definition: tm4c123gh6pm.h:713
#define GPIO_PORTF_DIR_R
Definition: tm4c123gh6pm.h:711
#define GPIO_PORTF_CR_R
Definition: tm4c123gh6pm.h:729
#define SYSCTL_RCGCGPIO_R
#define GPIO_PORTF_AMSEL_R
Definition: tm4c123gh6pm.h:730
#define GPIO_PORTF_AFSEL_R
Definition: tm4c123gh6pm.h:719
#define GPIO_PORTF_LOCK_R
Definition: tm4c123gh6pm.h:728
#define GPIO_PORTF_IM_R
Definition: tm4c123gh6pm.h:715
#define NVIC_PRI7_R
#define GPIO_PORTF_PCTL_R
Definition: tm4c123gh6pm.h:731
#define GPIO_PORTF_DEN_R
Definition: tm4c123gh6pm.h:727
#define GPIO_PORTF_PUR_R
Definition: tm4c123gh6pm.h:724
#define GPIO_PORTF_IEV_R
Definition: tm4c123gh6pm.h:714
#define GPIO_PORTF_IS_R
Definition: tm4c123gh6pm.h:712
#define SYSCTL_PRGPIO_R