SikendeRTOS
RTOS for ARM Cortex M3+ SoCs designed and written from scratch
Timer.c
Go to the documentation of this file.
1
7#include "Timer.h"
8#include "tm4c123gh6pm.h"
9
10void (*Task0A)(void);
11void (*Task0B)(void);
12void (*Task1A)(void);
13void (*Task1B)(void);
14void (*Task2A)(void);
15void (*Task2B)(void);
16void (*Task3A)(void);
17void (*Task3B)(void);
18void (*Task4A)(void);
19void (*Task4B)(void);
20
23uint32_t StartCritical(void);
24void EndCritical(uint32_t sr);
25
26
31void SysTick_Init(uint32_t period){
32 NVIC_ST_CTRL_R = 0; // disable SysTick during setup
33 NVIC_ST_CURRENT_R = 0; // any write to current clears it
34 NVIC_SYS_PRI3_R =(NVIC_SYS_PRI3_R&0x00FFFFFF)|0xD0000000; // priority 6
35 NVIC_SYS_PRI3_R =(NVIC_SYS_PRI3_R&0xFF00FFFF)|0x00E00000; // priority 7
36 NVIC_ST_RELOAD_R = period - 1; // reload value
37 NVIC_ST_CTRL_R = 0x00000007; // enable, core clock and interrupt arm
38}
39
40void Timer0A_Init(void (*task)(void), uint32_t period, uint32_t priority){
41 uint32_t sr = StartCritical();
42 SYSCTL_RCGCTIMER_R |= 0x01; // 0) activate TIMER0
43 Task0A = task;
44 TIMER0_CTL_R &= ~TIMER_CTL_TAEN; // 1) disable TIMER0A during setup
45 TIMER0_CFG_R = TIMER_CFG_32_BIT_TIMER; // 2) configure for 32-bit mode
46 TIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // 3) configure for periodic mode, default down-count settings
47 TIMER0_TAILR_R = period - 1; // 4) reload value
48 TIMER0_TAPR_R = 0; // 5) bus clock resolution
49 TIMER0_ICR_R = TIMER_ICR_TATOCINT; // 6) clear TIMER0A timeout flag
50 TIMER0_IMR_R |= TIMER_IMR_TATOIM; // 7) arm timeout interrupt
51 priority &= 0x07;
52 NVIC_PRI4_R = (NVIC_PRI4_R&0x00FFFFFF)|(priority << 29); // 8) priority 1
53 // interrupts enabled in the main program after all devices initialized
54 // vector number 35, interrupt number 19
55 NVIC_EN0_R |= 1<<19; // 9) enable IRQ 19 in NVIC
56 TIMER0_CTL_R |= TIMER_CTL_TAEN; // 10) enable TIMER0A
57 EndCritical(sr);
58}
59
60void Timer0B_Init(void (*task)(void), uint32_t period, uint32_t priority){
61 uint32_t sr = StartCritical();
62 SYSCTL_RCGCTIMER_R |= 0x01; // 0) activate TIMER0
63 Task0B = task;
64 TIMER0_CTL_R &= ~TIMER_CTL_TBEN; // 1) disable TIMER0B during setup
65 TIMER0_CFG_R = TIMER_CFG_32_BIT_TIMER; // 2) configure for 32-bit mode
66 TIMER0_TBMR_R = TIMER_TBMR_TBMR_PERIOD; // 3) configure for periodic mode, default down-count settings
67 TIMER0_TBILR_R = period - 1; // 4) reload value
68 TIMER0_TBPR_R = 0; // 5) bus clock resolution
69 TIMER0_ICR_R = TIMER_ICR_TBTOCINT; // 6) clear TIMER0B timeout flag
70 TIMER0_IMR_R |= TIMER_IMR_TBTOIM; // 7) arm timeout interrupt
71 priority &= 0x07;
72 NVIC_PRI5_R = (NVIC_PRI5_R&0xFFFFFF00)|(priority << 5); // 8) priority 1
73 // interrupts enabled in the main program after all devices initialized
74 // vector number 36, interrupt number 20
75 NVIC_EN0_R |= 1<<20; // 9) enable IRQ 20 in NVIC
76 TIMER0_CTL_R |= TIMER_CTL_TBEN; // 10) enable TIMER0B
77 EndCritical(sr);
78}
79
80void Timer1A_Init(void (*task)(void), uint32_t period, uint32_t priority){
81 uint32_t sr = StartCritical();
82 SYSCTL_RCGCTIMER_R |= 0x02; // 0) activate TIMER1
83 Task1A = task;
84 TIMER1_CTL_R &= ~TIMER_CTL_TAEN; // 1) disable TIMER1A during setup
85 TIMER1_CFG_R = TIMER_CFG_32_BIT_TIMER; // 2) configure for 32-bit mode
86 TIMER1_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // 3) configure for periodic mode, default down-count settings
87 TIMER1_TAILR_R = period-1; // 4) reload value
88 TIMER1_TAPR_R = 0; // 5) bus clock resolution
89 TIMER1_ICR_R = TIMER_ICR_TATOCINT; // 6) clear TIMER1A timeout flag
90 TIMER1_IMR_R |= TIMER_IMR_TATOIM; // 7) arm timeout interrupt
91 priority = (priority & 0x07) << 13; // mask priority (nvic bits 15-13)
92 NVIC_PRI5_R = (NVIC_PRI5_R&0xFFFF00FF)| (priority); // 8) priority
93
94 // interrupts enabled in the main program after all devices initialized
95 // vector number 37, interrupt number 21
96 NVIC_EN0_R |= 1<<21; // 9) enable IRQ 21 in NVIC
97 TIMER1_CTL_R |= TIMER_CTL_TAEN; // 10) enable TIMER1A
98 EndCritical(sr);
99}
100
101void Timer1B_Init(void (*task)(void), uint32_t period, uint32_t priority){
102 uint32_t sr = StartCritical();
103 SYSCTL_RCGCTIMER_R |= 0x02; // 0) activate TIMER1
104 Task1B = task;
105 TIMER1_CTL_R &= ~TIMER_CTL_TBEN; // 1) disable TIMER1B during setup
106 TIMER1_CFG_R = TIMER_CFG_32_BIT_TIMER; // 2) configure for 32-bit mode
107 TIMER1_TBMR_R = TIMER_TBMR_TBMR_PERIOD; // 3) configure for periodic mode, default down-count settings
108 TIMER1_TBILR_R = period-1; // 4) reload value
109 TIMER1_TBPR_R = 0; // 5) bus clock resolution
110 TIMER1_ICR_R = TIMER_ICR_TBTOCINT; // 6) clear TIMER1B timeout flag
111 TIMER1_IMR_R |= TIMER_IMR_TBTOIM; // 7) arm timeout interrupt
112 priority &= 0x07;
113 NVIC_PRI5_R = (NVIC_PRI5_R&0xFF00FFFF)| (priority << 21); // 8) priority
114
115 // interrupts enabled in the main program after all devices initialized
116 // vector number 38, interrupt number 22
117 NVIC_EN0_R |= 1<<22; // 9) enable IRQ 22 in NVIC
118 TIMER1_CTL_R |= TIMER_CTL_TBEN; // 10) enable TIMER1B
119 EndCritical(sr);
120}
121
122void Timer2A_Init(void (*task)(void), uint32_t period, uint32_t priority){
123 SYSCTL_RCGCTIMER_R |= 0x04; // 0) activate timer2
124 Task2A = task; // user function
125 TIMER2_CTL_R &= ~TIMER_CTL_TAEN; // 1) disable timer2A during setup
126 TIMER2_CFG_R = TIMER_CFG_32_BIT_TIMER; // 2) configure for 32-bit mode
127 TIMER2_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // 3) configure for periodic mode, default down-count settings
128 TIMER2_TAILR_R = period-1; // 4) reload value
129 TIMER2_TAPR_R = 0; // 5) bus clock resolution
130 TIMER2_ICR_R = TIMER_ICR_TATOCINT; // 6) clear timer2A timeout flag
131 TIMER2_IMR_R |= TIMER_IMR_TATOIM; // 7) arm timeout interrupt
132 priority &= 0x07;
133 NVIC_PRI5_R = (NVIC_PRI5_R&0x00FFFFFF)|(priority << 29); // 8) priority
134// interrupts enabled in the main program after all devices initialized
135// vector number 39, interrupt number 23
136 NVIC_EN0_R |= 1<<23; // 9) enable IRQ 23 in NVIC
137 TIMER2_CTL_R |= TIMER_CTL_TAEN; // 10) enable timer2A
138}
139
140void Timer2B_Init(void (*task)(void), uint32_t period, uint32_t priority){
141 SYSCTL_RCGCTIMER_R |= 0x04; // 0) activate timer2
142 Task2B = task; // user function
143 TIMER2_CTL_R &= ~TIMER_CTL_TBEN; // 1) disable timer2B during setup
144 TIMER2_CFG_R = TIMER_CFG_32_BIT_TIMER; // 2) configure for 32-bit mode
145 TIMER2_TBMR_R = TIMER_TBMR_TBMR_PERIOD; // 3) configure for periodic mode, default down-count settings
146 TIMER2_TBILR_R = period-1; // 4) reload value
147 TIMER2_TBPR_R = 0; // 5) bus clock resolution
148 TIMER2_ICR_R = TIMER_ICR_TBTOCINT; // 6) clear timer2B timeout flag
149 TIMER2_IMR_R |= TIMER_IMR_TBTOIM; // 7) arm timeout interrupt
150 priority &= 0x07;
151 NVIC_PRI6_R = (NVIC_PRI6_R&0xFFFFFF00)|(priority << 5); // 8) priority
152// interrupts enabled in the main program after all devices initialized
153// vector number 40, interrupt number 24
154 NVIC_EN0_R |= 1<<24; // 9) enable IRQ 24 in NVIC
155 TIMER2_CTL_R |= TIMER_CTL_TBEN; // 10) enable timer2B
156}
157
158void Timer3A_Init(void (*task)(void), uint32_t period, uint32_t priority){
159 uint32_t sr = StartCritical();
160 SYSCTL_RCGCTIMER_R |= 0x08; // 0) activate TIMER3
161 Task3A = task;
162 TIMER3_CTL_R &= ~TIMER_CTL_TAEN; // 1) disable TIMER3A during setup
163 TIMER3_CFG_R = TIMER_CFG_32_BIT_TIMER; // 2) configure for 32-bit mode
164 TIMER3_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // 3) configure for periodic mode, default down-count settings
165 TIMER3_TAILR_R = period - 1; // 4) reload value
166 TIMER3_TAPR_R = 0; // 5) bus clock resolution
167 TIMER3_ICR_R = TIMER_ICR_TATOCINT; // 6) clear TIMER3A timeout flag
168 TIMER3_IMR_R |= TIMER_IMR_TATOIM; // 7) arm timeout interrupt
169 priority &= 0x07;
170 NVIC_PRI8_R = (NVIC_PRI8_R&0x00FFFFFF)|(priority << 29); // 8) priority
171
172 #if JITTER
173 Timer3_Period = period;
174 #endif
175
176 // interrupts enabled in the main program after all devices initialized
177 // vector number 51, interrupt number 35
178 NVIC_EN1_R |= 1<<(35-32); // 9) enable IRQ 35 in NVIC
179 TIMER3_CTL_R |= TIMER_CTL_TAEN; // 10) enable TIMER3A
180 EndCritical(sr);
181}
182
183void Timer3B_Init(void (*task)(void), uint32_t period, uint32_t priority){
184 uint32_t sr = StartCritical();
185 SYSCTL_RCGCTIMER_R |= 0x08; // 0) activate TIMER3
186 Task3B = task;
187 TIMER3_CTL_R &= ~TIMER_CTL_TBEN; // 1) disable TIMER3B during setup
188 TIMER3_CFG_R = TIMER_CFG_32_BIT_TIMER; // 2) configure for 32-bit mode
189 TIMER3_TBMR_R = TIMER_TBMR_TBMR_PERIOD; // 3) configure for periodic mode, default down-count settings
190 TIMER3_TBILR_R = period - 1; // 4) reload value
191 TIMER3_TBPR_R = 0; // 5) bus clock resolution
192 TIMER3_ICR_R = TIMER_ICR_TBTOCINT; // 6) clear TIMER3A timeout flag
193 TIMER3_IMR_R |= TIMER_IMR_TBTOIM; // 7) arm timeout interrupt
194 priority &= 0x07;
195 NVIC_PRI9_R = (NVIC_PRI9_R&0xFFFFFF00)|(priority << 5); // 8) priority
196
197 // interrupts enabled in the main program after all devices initialized
198 // vector number 52, interrupt number 36
199 NVIC_EN1_R |= 1<<(36-32); // 9) enable IRQ 35 in NVIC
200 TIMER3_CTL_R |= TIMER_CTL_TBEN; // 10) enable TIMER3B
201 EndCritical(sr);
202}
203
204void Timer4A_Init(void (*task)(void), uint32_t period, uint32_t priority){
205 uint32_t sr = StartCritical();
206 SYSCTL_RCGCTIMER_R |= 0x10; // 0) activate TIMER4
207 Task4A = task;
208 TIMER4_CTL_R &= ~TIMER_CTL_TAEN; // 1) disable TIMER4A during setup
209 TIMER4_CFG_R = TIMER_CFG_32_BIT_TIMER; // 2) configure for 32-bit mode
210 TIMER4_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // 3) configure for periodic mode, default down-count settings
211 TIMER4_TAILR_R = period - 1; // 4) reload value
212 TIMER4_TAPR_R = 0; // 5) bus clock resolution
213 TIMER4_ICR_R = TIMER_ICR_TATOCINT; // 6) clear TIMER4A timeout flag
214 TIMER4_IMR_R |= TIMER_IMR_TATOIM; // 7) arm timeout interrupt
215 priority &= 0x07;
216
217 #if JITTER
218 Timer4_Period = period;
219 #endif
220
221 NVIC_PRI17_R = (NVIC_PRI17_R&0xFF00FFFF);
222 NVIC_PRI17_R = (NVIC_PRI17_R | (priority << 21)); // 8) priority
223 // interrupts enabled in the main program after all devices initialized
224 // vector number 86, interrupt number 70
225 NVIC_EN2_R = 1<<(70-64); // 9) enable IRQ 70 in NVIC
226 TIMER4_CTL_R |= TIMER_CTL_TAEN; // 10) enable TIMER4A
227 EndCritical(sr);
228}
229
230void Timer4B_Init(void (*task)(void), uint32_t period, uint32_t priority){
231 uint32_t sr = StartCritical();
232 SYSCTL_RCGCTIMER_R |= 0x10; // 0) activate TIMER4
233 Task4B = task;
234 TIMER4_CTL_R &= ~TIMER_CTL_TBEN; // 1) disable TIMER4B during setup
235 TIMER4_CFG_R = TIMER_CFG_32_BIT_TIMER; // 2) configure for 32-bit mode
236 TIMER4_TBMR_R = TIMER_TBMR_TBMR_PERIOD; // 3) configure for periodic mode, default down-count settings
237 TIMER4_TBILR_R = period - 1; // 4) reload value
238 TIMER4_TBPR_R = 0; // 5) bus clock resolution
239 TIMER4_ICR_R = TIMER_ICR_TBTOCINT; // 6) clear TIMER4B timeout flag
240 TIMER4_IMR_R |= TIMER_IMR_TBTOIM; // 7) arm timeout interrupt
241 priority &= 0x07;
242 NVIC_PRI17_R = (NVIC_PRI17_R&0x00FFFFFF);
243 NVIC_PRI17_R = (NVIC_PRI17_R | (priority << 29)); // 8) priority
244 // interrupts enabled in the main program after all devices initialized
245 // vector number 87, interrupt number 71
246 NVIC_EN2_R = 1<<(71-64); // 9) enable IRQ 71 in NVIC
247 TIMER4_CTL_R |= TIMER_CTL_TBEN; // 10) enable TIMER4B
248 EndCritical(sr);
249}
250
251
252
253
254
256 TIMER0_ICR_R = TIMER_ICR_TATOCINT;// acknowledge timer0A timeout
257 Task0A();
258}
259
261 TIMER0_ICR_R = TIMER_ICR_TBTOCINT;// acknowledge timer0B timeout
262 Task0B();
263}
264
266 TIMER1_ICR_R = TIMER_ICR_TATOCINT;// acknowledge timer1A timeout
267 Task1A();
268}
269
271 TIMER1_ICR_R = TIMER_ICR_TBTOCINT;// acknowledge timer1B timeout
272 Task1B();
273}
274
276 TIMER2_ICR_R = TIMER_ICR_TATOCINT;// acknowledge timer2A timeout
277 Task2A();
278}
279
281 TIMER2_ICR_R = TIMER_ICR_TBTOCINT;// acknowledge timer2B timeout
282 Task2B();
283}
284
286 TIMER3_ICR_R = TIMER_ICR_TATOCINT;// acknowledge timer3A timeout
287 Task3A();
288}
289
291 TIMER3_ICR_R = TIMER_ICR_TBTOCINT;// acknowledge timer3B timeout
292 Task3B();
293}
294
296 TIMER4_ICR_R = TIMER_ICR_TATOCINT;// acknowledge timer4A timeout
297 Task4A();
298}
299
301 TIMER4_ICR_R = TIMER_ICR_TBTOCINT;// acknowledge timer4B timeout
302 Task4B();
303}
304
void(* Task1B)(void)
Definition: Timer.c:13
void Timer2B_Handler(void)
Definition: Timer.c:280
void Timer0A_Init(void(*task)(void), uint32_t period, uint32_t priority)
Definition: Timer.c:40
void(* Task4A)(void)
Definition: Timer.c:18
void Timer1B_Init(void(*task)(void), uint32_t period, uint32_t priority)
Definition: Timer.c:101
void Timer3B_Handler(void)
Definition: Timer.c:290
void Timer1A_Handler(void)
Definition: Timer.c:265
void(* Task1A)(void)
Definition: Timer.c:12
void(* Task0A)(void)
Definition: Timer.c:10
void Timer0A_Handler(void)
Definition: Timer.c:255
void(* Task4B)(void)
Definition: Timer.c:19
void(* Task2A)(void)
Definition: Timer.c:14
void Timer4A_Init(void(*task)(void), uint32_t period, uint32_t priority)
Definition: Timer.c:204
void Timer3A_Handler(void)
Definition: Timer.c:285
void(* Task2B)(void)
Definition: Timer.c:15
void Timer1B_Handler(void)
Definition: Timer.c:270
void Timer2A_Handler(void)
Definition: Timer.c:275
void Timer4B_Init(void(*task)(void), uint32_t period, uint32_t priority)
Definition: Timer.c:230
uint32_t StartCritical(void)
void Timer4B_Handler(void)
Definition: Timer.c:300
void Timer2B_Init(void(*task)(void), uint32_t period, uint32_t priority)
Definition: Timer.c:140
void Timer1A_Init(void(*task)(void), uint32_t period, uint32_t priority)
Definition: Timer.c:80
void Timer0B_Init(void(*task)(void), uint32_t period, uint32_t priority)
Definition: Timer.c:60
void Timer3A_Init(void(*task)(void), uint32_t period, uint32_t priority)
Definition: Timer.c:158
void EnableInterrupts(void)
void EndCritical(uint32_t sr)
void(* Task3A)(void)
Definition: Timer.c:16
void(* Task0B)(void)
Definition: Timer.c:11
void DisableInterrupts(void)
void Timer0B_Handler(void)
Definition: Timer.c:260
void Timer3B_Init(void(*task)(void), uint32_t period, uint32_t priority)
Definition: Timer.c:183
void(* Task3B)(void)
Definition: Timer.c:17
void Timer4A_Handler(void)
Definition: Timer.c:295
void Timer2A_Init(void(*task)(void), uint32_t period, uint32_t priority)
Definition: Timer.c:122
void SysTick_Init(uint32_t period)
Definition: Timer.c:31
Periodic Timer setup for TM4c123.
Register location header of TM4C123GH6PM.
#define TIMER2_TAPR_R
#define TIMER1_TBILR_R
#define TIMER3_TBMR_R
#define NVIC_EN0_R
#define TIMER1_IMR_R
Definition: tm4c123gh6pm.h:996
#define TIMER2_TAMR_R
#define TIMER0_TAMR_R
Definition: tm4c123gh6pm.h:959
#define NVIC_PRI9_R
#define NVIC_ST_RELOAD_R
#define TIMER2_CFG_R
#define TIMER3_TAILR_R
#define TIMER2_CTL_R
#define NVIC_EN1_R
#define TIMER0_TAILR_R
Definition: tm4c123gh6pm.h:967
#define TIMER4_TBMR_R
#define NVIC_EN2_R
#define TIMER2_TAILR_R
#define TIMER4_CFG_R
#define TIMER0_CTL_R
Definition: tm4c123gh6pm.h:961
#define TIMER2_ICR_R
#define TIMER4_TAPR_R
#define TIMER1_CFG_R
Definition: tm4c123gh6pm.h:991
#define TIMER3_CTL_R
#define TIMER2_TBILR_R
#define TIMER3_TBPR_R
#define TIMER0_CFG_R
Definition: tm4c123gh6pm.h:958
#define NVIC_PRI5_R
#define TIMER_TAMR_TAMR_PERIOD
#define NVIC_ST_CURRENT_R
#define TIMER0_TBMR_R
Definition: tm4c123gh6pm.h:960
#define NVIC_PRI8_R
#define TIMER4_CTL_R
#define NVIC_PRI4_R
#define TIMER3_TAMR_R
#define TIMER4_TAMR_R
#define TIMER1_TBPR_R
#define TIMER3_CFG_R
#define TIMER3_TAPR_R
#define TIMER4_IMR_R
#define NVIC_PRI6_R
#define TIMER0_ICR_R
Definition: tm4c123gh6pm.h:966
#define TIMER0_TBPR_R
Definition: tm4c123gh6pm.h:972
#define TIMER1_TAMR_R
Definition: tm4c123gh6pm.h:992
#define TIMER_IMR_TBTOIM
#define TIMER3_IMR_R
#define TIMER_IMR_TATOIM
#define TIMER2_TBMR_R
#define TIMER1_TAPR_R
#define TIMER_ICR_TATOCINT
#define TIMER1_TAILR_R
#define TIMER_CTL_TBEN
#define TIMER1_ICR_R
Definition: tm4c123gh6pm.h:999
#define TIMER0_TBILR_R
Definition: tm4c123gh6pm.h:968
#define TIMER4_ICR_R
#define TIMER4_TBILR_R
#define TIMER0_IMR_R
Definition: tm4c123gh6pm.h:963
#define SYSCTL_RCGCTIMER_R
#define TIMER3_ICR_R
#define NVIC_ST_CTRL_R
#define NVIC_SYS_PRI3_R
#define TIMER_ICR_TBTOCINT
#define TIMER1_TBMR_R
Definition: tm4c123gh6pm.h:993
#define TIMER0_TAPR_R
Definition: tm4c123gh6pm.h:971
#define TIMER_TBMR_TBMR_PERIOD
#define TIMER_CTL_TAEN
#define TIMER3_TBILR_R
#define NVIC_PRI17_R
#define TIMER1_CTL_R
Definition: tm4c123gh6pm.h:994
#define TIMER2_IMR_R
#define TIMER4_TAILR_R
#define TIMER_CFG_32_BIT_TIMER
#define TIMER4_TBPR_R
#define TIMER2_TBPR_R